Restricted Moduli Symmetrical Signed Residue Addition: Part I
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Date
2010-11-23
Authors
Daikpor, M.N
Adegbenro, O
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Abstract
In this paper we propose a scheme for the design of a Symmetrical Multiple Valued Logic (SMVL) arithmetic
circuit based on the use of restricted moduli Symmetrical Signed digit Residue Number system (SSRNS). Sign and overflow detection as welI as magnitude comparison operations are accomplished without recourse to the traditional complex Mixed Radix number System (MRS) conversion process and multiplicative inverse computation. The method is particularly general purpose systems oriented. Addition operations are executed economicalIy, fast and at constant speed.
Description
Conference Papers
Keywords
Magnitude , Conversion , Number System
Citation
Daikpor, M.N and Adegbenro, O (2010) Restricted Moduli Symmetrical Signed Residue Addition: Part I. 18th Telecommunications Forum TELFOR, Held at Serbia, Belgrade.