Radix-7 Signed Digit Element Finite Field Arithemetic
dc.contributor.author | Daikpor, M.N | |
dc.contributor.author | Adegbenro, O | |
dc.date.accessioned | 2016-05-03T10:08:12Z | |
dc.date.available | 2016-05-03T10:08:12Z | |
dc.date.issued | 2007-11-24 | |
dc.description | Conference Papers | en_US |
dc.description.abstract | In this contribution we present radix - 7 signed digit element finite fields as a gateway to multiple-value logic public key cryptographic systems design. We also construct signed digit Galois Field SGF(72). A radix - 7 signed digit element finite field multiplication circuit is implemented using complementary pass-gate derived 7- value. T-gate (1] . | en_US |
dc.identifier.citation | Daikpor, M.N and Adegbenro, O (2007) Radix-7 Signed Digit Element Finite Field Arithemetic. IEEE International Conference on Signal Processing and Communications (ICSPC), Held at Dubai, United Emirates | en_US |
dc.identifier.uri | http://ir.unilag.edu.ng:8080/xmlui/handle/123456789/628 | |
dc.language.iso | en | en_US |
dc.relation.ispartofseries | Conference Papers; | |
dc.subject | Multiple-valued logic | en_US |
dc.subject | Arithemetic | en_US |
dc.subject | Element | en_US |
dc.title | Radix-7 Signed Digit Element Finite Field Arithemetic | en_US |
dc.type | Presentation | en_US |
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