Restricted Moduli Symmetrical Signed Residue Addition: Part I
| dc.contributor.author | Daikpor, M.N | |
| dc.contributor.author | Adegbenro, O | |
| dc.date.accessioned | 2016-05-03T10:06:07Z | |
| dc.date.available | 2016-05-03T10:06:07Z | |
| dc.date.issued | 2010-11-23 | |
| dc.description | Conference Papers | en_US |
| dc.description.abstract | In this paper we propose a scheme for the design of a Symmetrical Multiple Valued Logic (SMVL) arithmetic circuit based on the use of restricted moduli Symmetrical Signed digit Residue Number system (SSRNS). Sign and overflow detection as welI as magnitude comparison operations are accomplished without recourse to the traditional complex Mixed Radix number System (MRS) conversion process and multiplicative inverse computation. The method is particularly general purpose systems oriented. Addition operations are executed economicalIy, fast and at constant speed. | en_US |
| dc.identifier.citation | Daikpor, M.N and Adegbenro, O (2010) Restricted Moduli Symmetrical Signed Residue Addition: Part I. 18th Telecommunications Forum TELFOR, Held at Serbia, Belgrade. | en_US |
| dc.identifier.uri | http://ir.unilag.edu.ng:8080/xmlui/handle/123456789/627 | |
| dc.language.iso | en | en_US |
| dc.relation.ispartofseries | Conference Papers; | |
| dc.subject | Magnitude | en_US |
| dc.subject | Conversion | en_US |
| dc.subject | Number System | en_US |
| dc.title | Restricted Moduli Symmetrical Signed Residue Addition: Part I | en_US |
| dc.type | Presentation | en_US |
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